1. Field of the Invention
The present invention relates to a voltage control circuit which prevents a thermal damage even if a short-circuit fault occurs.
2. Background Information
A voltage control circuit (voltage regulator) is a circuit that is connected between a power supply and a fed circuit. The voltage control circuit conducts a control so as to hold a voltage value that is output from the voltage control circuit to the fed circuit constant even if a voltage value that is input from the power supply to the voltage control circuit is varied.
When this type of the voltage control circuit is incorporated into a power supply portion, it is possible to apply a voltage having a constant voltage value to the fed circuit even if an output voltage of the power supply (for example, a battery) is varied. Accordingly, a voltage control circuit of a monolithic IC is incorporated into the power supply portion of a portable device such as a cell phone, a game machine, or a notebook computer.
Now, the basic circuit configuration and operation principle of the voltage control circuit will be described with reference to FIG. 5. As shown in FIG. 5, a voltage control circuit 1 includes a voltage control p-channel MOS transistor 10, a voltage divider resistor circuit 20, and a transistor control circuit 30 as main members.
The voltage control p-channel MOS transistor 10 has an input terminal (source) connected to a voltage input terminal 11 of the voltage control circuit 1, and an output terminal (drain) connected to a voltage output terminal 12 of the voltage control circuit 1.
The voltage control p-channel MOS transistor 10 has such a characteristic that conduction resistance is increased as the voltage value of a control voltage Vc that is input to a control terminal (gate) is increased, and the conduction resistance is decreased as the voltage value of the control voltage Vc that is input to the control terminal (gate) is decreased. The “conduction resistance” means a resistance between the input terminal (source) and the output terminal (drain) obtained when the voltage control p-channel MOS transistor 10 is rendered conductive.
The voltage input terminal 11 of the voltage control circuit 1 is input with a supply voltage (input voltage) Vin from a power supply (for example, a battery). The input voltage Vin has a voltage value controlled by the voltage control p-channel MOS transistor 10, and an output voltage Vout that becomes a predetermined set voltage value is output from the voltage output terminal 12 of the voltage control circuit 1. A voltage control manner using the voltage control p-channel MOS transistor 10 will be described later.
Also, the voltage output terminal 12 is connected to a fed circuit (not shown), and a voltage that becomes the set voltage value is applied to the fed circuit.
The voltage divider resistor circuit 20 is designed so as to connect a voltage divider resistor 21 and a voltage divider resistor 22 in series. One end (high voltage end) of the voltage divider resistor circuit 20 is connected to the voltage output terminal 12, and the other end thereof (low voltage end) is connected to a ground potential.
The voltage divider resistor circuit 20 outputs a divided voltage Vp obtained by dividing the output voltage Vout which is output from the voltage output terminal 12 by the voltage divider resistors 21 and 22. The divided voltage Vp is a voltage that is applied to the voltage divider resistor 22, and is represented by the following expression when it is assumed that a resistance of the voltage divider resistor 21 is R21, and a resistance of the voltage divider resistor 22 is R22.Vp=Vout·[R22/(R21+R22)]
The transistor control circuit 30 has a differential amplifier (operational amplifier) 31 and a reference voltage source 32. A non-inverting input terminal (positive terminal) of the differential amplifier 31 is input with the divided voltage Vp, and an inverting input terminal (negative terminal) of the differential amplifier 31 is input with a reference voltage Vref that is output from the reference voltage source 32.
The differential amplifier 31 outputs the control voltage Vc according to a deviation between the divided voltage Vp and the reference voltage Vref. The control voltage Vc is input to the gate of the voltage control p-channel MOS transistor 10.
The operation principle of holding the voltage value of the output voltage Vout that is output from the voltage output terminal 12 to the set value (constant value) by the aid of the voltage control circuit (voltage regulator) 1 structured above will be described below.
For example, when the voltage value of the output voltage Vout increases beyond the set value (constant value), the voltage value of the divided voltage Vp also increases. As a result, the voltage value of the control voltage Vc increases. When the voltage value of the control voltage Vc increases, the conduction resistance of the voltage control p-channel MOS transistor 10 increases, and the output voltage Vout decreases due to the increase in the conduction resistance. Then, the voltage value of the output voltage Vout is returned to the set value (constant value).
On the contrary, for example, when the voltage value of the output voltage Vout is made lower than the set value (constant value), the voltage value of the divided voltage Vp also decreases. As a result, the voltage value of the control voltage Vc decreases. When the voltage value of the control voltage Vc decreases, the conduction resistance of the voltage control p-channel MOS transistor 10 decreases, and the output voltage Vout increases due to the decrease in the conduction resistance. Then, the voltage value of the output voltage Vout is returned to the set value (constant value).
In this way, the voltage value of the output voltage Vout is held to the set value (constant value). The set value (constant value) of the output voltage Vout is represented by the following expression.Vout=Vref·[(R21+R22)/R22]
Incidentally, when a short-circuit fault occurs in the fed circuit that is connected to the voltage output terminal 12 or the like, the voltage value of the voltage at the voltage output terminal 12 is rapidly decreased down to the voltage value of the ground potential or a voltage value close to the ground potential. When the voltage value of the voltage output terminal 12 is remarkably decreased due to the short-circuit fault in this way, the voltage value of the divided voltage Vp as well as the voltage value of the control voltage Vc is remarkably decreased. When the voltage value of the control voltage Vc is remarkably decreased, the conduction resistance of the voltage control p-channel MOS transistor 10 is remarkably decreased. As a result, a current value of the current that flows in the voltage control p-channel MOS transistor 10 is remarkably increased.
When a large current flows in the voltage control p-channel MOS transistor 10 due to the short-circuit fault as described above, a heat generation that is attributable to the large current increases, resulting in a risk that an IC package into which the voltage control circuit 1 is incorporated is thermally damaged. That is, due to the short-circuit fault, a large amount of the heat is generated beyond the permissible heat resistance capacity of the IC package, and there is a risk that the IC such as the voltage control circuit 1 is thermally damaged.
Under the circumstances, there has been developed a voltage control circuit that is added with a short-circuit protection circuit that limits a current which flows in the control MOS transistor even if the short-circuit fault occurs (for example, refer to JP 07-74976 B).
Next, a voltage control circuit (voltage regulator) 1A with the short-circuit protection circuit will be described with reference to FIG. 6. The same parts as those in FIG. 5 are denoted by identical reference numerals, and their overlapping description will be omitted.
As shown in FIG. 6, the voltage control circuit (voltage regulator) 1A further includes a monitor circuit 40, an inverter circuit 50, and a transistor control MOS transistor 60 in addition to the voltage control p-channel MOS transistor 10, the voltage divider resistor circuit 20, and the transistor control circuit 30.
The monitor circuit 40, the inverter circuit 50, and the transistor control MOS transistor 60 constitute a short-circuit protection circuit.
The monitor circuit 40 is designed so as to connect a monitor MOS transistor 41 and a monitor resistor 42 in series, and a connection point of the drain of the monitor MOS transistor 41 and the monitor resistor 42 is represented as a monitor voltage output point 43.
The monitor circuit 40 is connected in parallel to the voltage control p-channel MOS transistor 10. That is, one end (high voltage end) of the monitor circuit 40 is connected to the source of the voltage control p-channel MOS transistor 10, and the other end (low voltage end) of the monitor circuit 40 is connected to the drain of the voltage control p-channel MOS transistor 10.
The monitor MOS transistor 41 of the monitor circuit 40 has such a characteristic that the conduction resistance increases as the voltage value of the voltage that is input to the control terminal (gate) thereof increases, and the conduction resistance decreases as the voltage value of the voltage that is input to the control terminal (gate) thereof decreases.
The gate of the monitor MOS transistor 41 is connected to the output terminal of the differential amplifier 31 in the transistor control circuit 30.
Further, when the monitor MOS transistor 41 is described in comparison with the voltage control p-channel MOS transistor 10, both of the MOS transistors 10 and 41 are equal to each other in the channel length. Also, the channel width of the monitor MOS transistor 41 is smaller than the channel width of the voltage control p-channel MOS transistor 10.
In this example, when it is assumed that a division value obtained by dividing the “channel width of the voltage control p-channel MOS transistor 10” by the “channel width of the monitor MOS transistor 41” is a channel width ratio α, the channel width ratio α is, for example, 100.
Accordingly, in the case where both of the MOS transistors 10 and 41 are rendered conductive, the current value of the current that flows in the monitor MOS transistor 41 is a small current value obtained by multiplying the current value of the current that flows in the voltage control p-channel MOS transistor 10 by 1/α (for example, 1/100).
For that reason, in the case where the current that flows in the voltage control p-channel MOS transistor 10 increases or decreases, the current value of the current that flows in the monitor MOS transistor 41 also increases or decreases. Moreover, the current values of both of the MOS transistors 10 and 41 increase or decrease while keeping a proportional relationship. In other words, the current that flows in the voltage control p-channel MOS transistor 10 is scaled to 1/α (for example, 1/100) times, and monitored by the monitor MOS transistor 41.
The inverter circuit 50 is designed so as to connect an inverter resistor 51 and an inverter MOS transistor 52 in series, and a connection point of the inverter resistor 51 and the drain of the inverter MOS transistor 52 is represented by an inverter output point 53.
The inverter circuit 50 is connected in parallel to the voltage control p-channel MOS transistor 10. In other words, one end (high voltage end) of the inverter circuit 50 is connected to the source of the voltage control p-channel MOS transistor 10, and the other end (low voltage end) of the inverter circuit 50 is connected to the drain of the voltage control p-channel MOS transistor 10.
The gate of the inverter MOS transistor 52 is connected to the monitor voltage output point 43 of the monitor circuit 40.
The transistor control MOS transistor 60 has a source connected to the voltage input terminal 11, and a drain connected to the gate of the voltage control p-channel MOS transistor 10 and the gate of the monitor MOS transistor 41. The gate of the transistor control MOS transistor 60 is connected to the inverter output point 53 of the inverter circuit 50.
The transistor control MOS transistor 60 has such a characteristic that the conduction resistance increases as the voltage value of the voltage that is input to the control terminal (gate) thereof increases, and the conduction resistance decreases as the voltage value of the voltage that is input to the control terminal (gate) thereof decreases.
In the voltage control circuit 1A thus configured, when the control voltage Vc is applied to the gate of the voltage control p-channel MOS transistor 10 and the gate of the monitor MOS transistor 41 from the transistor control circuit 30, both of the MOS transistors 10 and 41 are rendered conductive.
In a normal state where no short-circuit fault occurs, the inverter MOS transistor 52 and the transistor control MOS transistor 60 are rendered nonconductive.
In a state where the input voltage Vin is input to the voltage input terminal 11 and the fed circuit is connected to the voltage output terminal 12, when both of the MOS transistors 10 and 41 are rendered conductive, the current flows in the voltage control p-channel MOS transistor 10 and the monitor MOS transistor 41.
In this situation, when it is assumed that a current that flows in the voltage control p-channel MOS transistor 10 is i10 and a current that flows in the monitor MOS transistor 41 (monitor circuit 40) is i40, a relationship of i10/α=i40 is established.
On the other hand, when the short-circuit fault occurs in the fed circuit that is connected to the voltage output terminal 12 or the like, the current i10 that flows in the voltage control p-channel MOS transistor 10 rapidly increases, and the current i40 that flows in the monitor MOS transistor 41 (monitor circuit 40) also rapidly increases in proportion to the current i10 as described above.
When the current that flows in the monitor circuit 40 rapidly increases, a monitor voltage Vm (voltage generated by allowing the current i40 to flow in the monitor resistor 42) which is applied to the monitor resistor 42 rapidly increases. The monitor voltage Vm is applied to the inverter MOS transistor 52 through the monitor voltage output point 43. For that reason, when the monitor voltage Vm exceeds a threshold voltage Vt of the inverter MOS transistor 52, the inverter MOS transistor 52 is rendered conductive.
When the inverter MOS transistor 52 is rendered conductive as described above, the potential of the inverter output point 53 changes from the high potential (potential equivalent to the potential of the voltage input terminal 11) to the low potential (potential equivalent to the potential (ground potential) of the voltage output terminal 12).
When the potential of the inverter output point 53 changes (inverts) from the high potential to the low potential, the potential that is input to the gate of the transistor control MOS transistor 60 also changes from the high potential to the low potential, and the conduction resistance of the transistor control MOS transistor 60 is decreased.
When the conduction resistance of the transistor control MOS transistor 60 becomes low, the transistor control MOS transistor 60 adjusts the voltage value of the input voltage Vin that has been input to the source according to the value of the conduction resistance, and outputs an additional control voltage Va whose voltage value has been adjusted from the drain. The additional control voltage Va is input to the gate of the voltage control p-channel MOS transistor 10.
Consequently, when the short-circuit fault occurs, the gate of the voltage control p-channel MOS transistor 10 is applied with not only the control voltage Vc that has been output from the transistor control circuit 30, but also the additional control voltage Va that has been output from the transistor control MOS transistor 60.
As described above, the voltage control p-channel MOS transistor 10 is applied with not only the control voltage Vc but also the additional control voltage Va, so the conduction resistance of the voltage control p-channel MOS transistor 10 rapidly increases. Because the conduction resistance of the voltage control p-channel MOS transistor 10 rapidly increases, the current i10 that flows in the voltage control p-channel MOS transistor 10 is also rapidly suppressed, and the current value of the current i10 is decreased.
As a result, even if the short-circuit fault occurs, the current value of the current that flows in the voltage control p-channel MOS transistor 10 can be suppressed, thereby preventing the thermal damage from occurring due to the short-circuit current.
FIG. 7 is a characteristic diagram showing a relationship between the current that flows in the voltage control p-channel MOS transistor 10 (an output current that is output from the voltage output terminal 12) and the output voltage Vout that is output from the voltage output terminal 12 in the voltage control circuit 1A added with the short-circuit protection circuit.
As shown in FIG. 7, when the output voltage Vout is decreased, the output current is also decreased with the decreased voltage in a state where the output current is the maximum current Im. Then, when the output voltage Vout becomes zero, that is, when the voltage output terminal 12 is short-circuited to the ground potential, the output current becomes a holding current Is.
The voltage-current characteristic shown in FIG. 7 is called “fold-back drooping characteristic” because of its shape.
Because the source potential (the potential of the voltage output terminal 12) of the inverter MOS transistor 52 is different from the ground potential, the “Fold-back drooping characteristic” is produced by varying the threshold voltage of the inverter MOS transistor 52 due to the back gate effect.
In this example, when it is assumed that the threshold voltage of the inverter MOS transistor 52 is Vt, the variation of the threshold voltage due to the back gate effect is ΔVt, and the resistance of the monitor resistor 42 is R42, the maximum current Im and the holding current Is are represented by the following expressions, respectively.Im=(Vt+ΔVt)/R42Is=Vt/R42
In the case where a short-circuit fault occurs, the conventional voltage control circuit 1A shown in FIG. 6 controls the resistance of the voltage control p-channel MOS transistor 10 to be larger, to thereby suppress the current value of the current that flows in the voltage control circuit 1A (the current that flows in the voltage control p-channel MOS transistor 10). More specifically, the current value of the current that flows in the voltage control circuit 1A when the short-circuit fault occurs (the current that flows in the voltage control p-channel MOS transistor 10) becomes a current value indicated by the holding current Is.
For that reason, in the case where the short-circuit fault continues, heat corresponding to an electric power represented by the following expression (1) continues to generate in the voltage control circuit 1A.[Input Voltage Vin]×[Holding current Is]  (1)
Moreover, the current value of the holding current Is in the embodiment shown in FIG. 6 is fixed to a predetermined current value (refer to FIG. 7).
Incidentally, the voltage control circuit is used in diverse industrial fields (for example, a field such as an on-vehicle regulator or a large-current regulator), and the voltage value of the input voltage that is input to the voltage input terminal of the voltage control circuit becomes large depending on an applied industrial field.
In the case where the voltage value of the input voltage that is input to the voltage control circuit is large, even if the current value of the current that flows in the voltage control circuit is suppressed to the current value indicated by the holding current Is, the generated voltage (Vin×Is) is increased, and the calorific value of the IC package into which the voltage control circuit has been incorporated becomes large as is apparent from the expression (1).
However, the permissible heat resistant capacity per se of the IC package is not changed as it was.
As a result, in the case where the voltage value of the input voltage that is input to the voltage control circuit is large, there is a risk that heat that exceeds the permissible heat resistant capacity of the IC package is generated, and the IC of the voltage control circuit or the like is thermally damaged.